The present invention relates generally to semiconductor storage devices, and more particularly to sensing circuitry commonly used between a plurality of banks in a semiconductor storage device.
Semiconductor storage devices, such as a Dynamic Random Access Memory (DRAM) store data on storage capacitors in a storage cell. Data can be read from or written to a storage cell by charging or discharging a storage capacitor. Because the charge on a storage capacitor is very small, it is required to sense the charge using a sense amp when data is read from a particular storage cell. Such charging/discharging can prevent the semiconductor storage device from operating at speeds as high as the central processing unit (CPU) requesting the information from the semiconductor storage device.
In order to improve operating speeds, semiconductor storage devices have been developed that divide a memory array into a plurality of independently operated banks of memory cells. The banks are then operated simultaneously in a manner such that one bank can be transmitting or receiving data while another is being activated and having a row of data sensed in preparation for an access operation to or from the bank. Such a semiconductor storage device can be considered to be composed of separate memory chips because each of the banks can operate independently.
An example of a semiconductor storage device using a multi-bank structure is disclosed in Japanese Patent Application Laid-Open No. Hei 9-219091. The semiconductor storage device disclosed in Japanese Patent Application Laid-Open No. Hei 9-219091 is a synchronous DRAM (SDRAM) which operates in synchronization with an edge of an externally supplied clock. The SDRAM disclosed in Hei 9-219091 is composed of a small number of banks, such as four.
Because each of the banks can be independently operated, in order to simultaneously activate a plurality of banks, control circuits are provided separately for each bank. For each bank, separate signal lines for transmitting various signals from the control circuits to the banks must also be provided. Control circuits include a row decoder (X-address decoder) and a column decoder (Y-address decoder) that decode external address signals. Control circuits can also include buffers that receive external control and address signals, and a row of sense amplifiers for sensing the logic level stored in a row of memory cells. Control circuits can also include control circuits for generating timing signals that control the previously mentioned circuits under various modes of operation.
Even when control circuits and control signal lines are provided for each of the banks, significant adverse problems can be minimized as long as the number of banks remain as low as four. However, when the number of independently operating banks increases beyond four to, for example, sixteen, thirty-two, etc., an adverse problem of an increased chip size corresponding to the increased number of banks can be problematic. Particularly, the chip area occupied by timing control circuits can be significantly large as compared to the chip area occupied by other circuits. Thus, as higher speed operation is needed such that the number of independently operating banks increases, chip size can be adversely affected.
In the above example, commands are externally supplied to the semiconductor storage device. A command decoder can receive these commands. Timing control circuits can receive the decoded commands and generate respective timing control signals by appropriately delaying signals to give desired timings. The delay can be provided by a plurality of inverters connected in series. These chains of inverters can result in an increased chip area occupied by the timing control circuits. Because some of the timing control signals are to be supplied to other areas of the semiconductor storage device or to a large number of circuits within a bank, the final driver stage needs a large current driving capability. This can require the final driver stage to include large sized transistors, which can further increase chip size.
In view of the above, a portion of control circuits provided for each of the banks is often shared. One such scheme includes a semiconductor storage device in which sense amplifier circuits are shared by adjacent banks. Such a configuration will now be described with reference to a number of drawings.
Referring now to FIG. 10, a block schematic diagram of a semiconductor storage device, having sense amplifiers shared by adjacent banks, is set forth and designated by the general reference character 1000. Semiconductor storage device 1000 illustrates components associated with bank activation up to sensing data from a row of memory cells in a bank. Other components that are included in a DRAM, in general, and known to those skilled in the art, have been omitted. Such circuits include, respective memory cells, precharging circuits, column (Y-address) decoders, column selection switches, input/output (I/O) lines, read/write amplifiers, output buffers, I/O pads, etc have been omitted from the illustration for clarity.
Semiconductor storage device 1000 includes sixteen banks (B0 to B15). Each bank (B0 to B15) has an identical configuration. Each bank (B0 to B15) includes a plurality of word lines (not shown) arranged along the row direction and a plurality of bit line pairs (partially shown) arranged in a column direction. Memory cells (not shown) are provided at cross-points of the word lines and the bit lines.
When a row address activation signal RAA becomes active (high in this case), a timing control circuit 1 activates an address enable signal AE and a sense enable signal SE (both high) at predetermined timings. These timings will be explained more in detail in accordance with the description of the present invention.
Row address buffer 2 receives an external address signal ADR and generates a row address signal RA when address enable signal AE becomes active (high).
Bank decoder 3 activates one of bank selection signal (BS0 to BS15) according to the value of a bank address included in address signal ADR.
Bank enable signal generation circuits (EC0 to EC15) are provided to correspond to banks (B0 to B15) respectively. A particular bank enable signal generation circuit ECn (where n can be an integer from 1 to 14) sets a bank enable signal BEn of the corresponding bank Bn to an enable state (high in this case) only when a bank selection signal BSn of the corresponding bank Bn is enabled (high) and both of the bank selection signals (BSnxe2x88x921 and BSn+1) of the adjacent banks are disabled (low). However, the end banks (B0 or B15) are set to an enbable state when a bank selection signal (BS0 or BS15) of the corresponding bank (B0 or B15) is enabled and bank selection signal (BS1 in the case of end bank B0 or BS14 in the case of end bank B15) of the adjacent bank is disabled. This prevents two adjacent banks from being active simultaneously and having a conflict at a shared sense amplifier row (SA0 to SA16).
Row decoders (DC0 to DC15) are provided to correspond to banks (B0 to B15), respectively. Each row decoder (DC0 to DC15) can decode a row address signal RA provided by row address buffer 2 when the corresponding bank enable signal (BE0 to BE15) becomes active. In this manner, a row decoder (DC0 to DC15) can activate only the word line specified by the row address signal RA among the word lines in the corresponding bank (B0 to B15).
Sense amplifier rows (SA0 to SA16) are provided at each side of banks (B0 to B15). Sense amplifier rows (SA1 to SA15) can be shared between two adjacent banks (B0 to B15). End sense amplifier rows (SA0 and SA16) can be unshared. Each sense amplifier bank (SA0 to SA16) can contain half as many sense amplifiers as there are bit line pairs in each bank (B0 to B15). Within a bank (B0 to B15) every other bit line pair can extend to be received by a sense amplifier in one of the adjacent sense amplifier rows (SA0 to SA16) while the other bit line pairs can each extend to be received by a sense amplifier in the other adjacent sense amplifier row (SA0 to SA16). Each Sense amplifier in the sense amplifier rows (SA0 to SA16) can sense small potential differences in the received bit line pair, and produces a logic level corresponding with the potential difference.
A pulse generation circuit 4 enables (high in this case) an overdrive signal VOP for a predetermined period (for example, several nanoseconds) when the sense enable signal SE is enabled.
An internal voltage driver 5 generates a sense amplifier drive voltage VINTA. Due to reduced transistor sizes and reduced power consumption desires, it is common to use a sense amplifier drive voltage VINTA that has a lower potential than an external power source voltage VCC. However, it is desired for the sense amplifier to sense data at a relatively fast speed. Thus, the current drive capabilities of internal voltage driver 5 can be increased by temporarily providing a low resistive path between external power source voltage VCC and sense amplifier drive voltage VINTA shortly before the beginning of the sensing operation. This can be thought of as an overdrive condition in which the current drive capability of the sense amplifiers can be improved. This is necessary because the bit lines can have relatively high capacitances due to a large number of memory cells being connected to each bit line. It is undesirable for the internal voltage driver 5 to continuously provide a high current source capability because this can increase power consumption. Once the sense amplifiers have achieved a high enough xe2x80x9csplitxe2x80x9d on the bit lines, the current source capability of internal voltage driver 5 can be reduced.
Referring now to FIG. 11, a circuit schematic diagram of internal voltage driver 5 is set forth. Internal voltage driver 5 includes a drive circuit 51, a comparator 52, and a overdrive circuit 53. Comparator 52 receives a reference voltage VREF at a negative input the sense amplifier drive voltage VINTA at a positive input. Comparator 52 produces a drive control signal 54 that can be received by the drive circuit 51. Drive circuit 51 receives the drive control signal 54 and generates a regulated sense amplifier drive voltage VINTA by modulating an impedance path between external voltage source VCC and sense amplifier drive voltage VINTA based on the drive control signal 54. Drive circuit 51 can be a pc-channel insulated gate field effect transistor (IGFET). When sense amplifier drive voltage VINTA is at a lower potential than reference voltage VREF, comparator 52 produces a low output which reduces the impedance path between the external voltage source VCC and the sense amplifier drive voltage VINTA. Thus, increasing the current drive of the internal voltage driver 5. When sense amplifier drive voltage VINTA is at a higher potential than reference voltage VREF, comparator 52 produces a high output which increases the impedance path between the external voltage source VCC and the sense amplifier drive voltage VINTA.
Internal voltage driver 5 includes a overdrive circuit 53. Overdrive circuit 53 receives overdrive signal VOP and provides a low impedance path between a low voltage source VSS and drive control signal 54 when overdrive signal VOP is in an overdrive enable state (high in this case) and a high impedance path when overdrive signal VOP is in an overdrive not enabled state. Thus, drive control signal 54 can be at a logic low when overdrive signal VOP is in the overdrive enable state. The logic low at drive control signal 54 causes drive circuit 51 to provide a low impedance path between VCC and sense amplifier drive voltage VINTA. However, when overdrive signal VOP is in an overdrive not enabled state, drive circuit is controlled by the comparator 52. Overdrive circuit 53 can be an n-channel IGFET.
As mentioned above, internal voltage driver 5 overdrives the sense amplifier drive voltage VINTA towards the external power source voltage VCC during a period when overdrive signal VOP is in an overdrive enable state (high). Thus, internal voltage driver 5 can provide increased current sourcing capabilities at an initial sensing period.
Referring once again to FIG. 10, semiconductor storage device 1000 also includes sense amplifier control circuits (SCD0 to SCD16) and sense amplifier drivers (DRD0 to DRD16). Sense amplifier control circuits (SCD0 to SCD16) receive sense enable signal SE and based upon the selected bank (B0 to B15) can activate a high sense drive line control signal (SEP0 to SEP16) and a low sense drive line control signal (SEN0 to SEN16).
Referring now to FIG. 12, a portion of semiconductor storage device 1000 is set forth in a block schematic diagram. The portion of semiconductor storage device 1000 illustrates three banks (B0 to B2), four sense amplifier rows (SA0 to SA3), and four conventional sense amplifier drivers (DRD0 to DRD3).
Conventional sense amplifier drivers (DRD0 to DRD3) receive high and low sense line drive signals (SEP0 to SEP3 and SEN0 to SEN3) from sense amplifier control circuit (SCD0 to SCD3), respectively. Conventional sense amplifier drivers (DRD0 to DRD3) also receive sense amplifier drive voltage VINTA and low voltage source VSS and can provide high and low sense line potentials to high and low sense line drive signals (SEP0 to SEP3 and SEN0 to SEN3), respectively.
Each sense amplifier driver (DRD0 to DRD3) includes a high sense amplifier drive circuit (TRSEP0 to TRSEP3), respectively. High sense amplifier drive circuit (TRSEP0 to TRSEP3) each can receive a high sense drive line control signal (SEP0 to SEP3), respectively. When a respective high sense drive line control signal (SEP0 to SEP3) is in an enabled state (logic low), the corresponding high sense amplifier drive circuit (TRSEP0 to TRSEP3) provides a low impedance between sense amplifier drive voltage VINTA and the respective high sense amplifier drive line (SAP0 to SAP3). When a respective high sense drive line control signal (SEP0 to SEP3) is in a not enabled state (logic high), the corresponding high sense amplifier drive circuit (TRSEP0 to TRSEP3) provides a high impedance between sense amplifier drive voltage VINTA and the respective high sense amplifier drive line (SAP0 to SAP3). Each high sense amplifier drive circuit (TRSEP0 to TRSEP3) can be a p-channel IGFET.
Each sense amplifier driver (DRD0 to DRD3) also includes a low sense amplifier drive circuit (TRSEN0 to TRSEN3), respectively. Low sense amplifier drive circuit (TRSEN0 to TRSEN3) each can receive a low sense drive line control signal (SEN0 to SEN3), respectively. When a respective low sense drive line control signal (SEN0 to SEN3) is in an enabled state (logic high), the corresponding low sense amplifier drive circuit (TRSEN0 to TRSEN3) provides a low impedance between low voltage source VSS and the respective low sense amplifier drive line (SAN0 to SAN3). When a respective low sense line drive signal (SEN0 to SEN3) is in a not enabled state (logic low), the corresponding low sense amplifier drive circuit (TRSEN0 to TRSEN3) provides a high impedance between low voltage source VSS and the respective low sense amplifier drive line (SAN0 to SAN3). Each low sense amplifier drive circuit (TRSEN0 to TRSEN3) can be a n-channel IGFET.
The operation of the semiconductor storage device 1000 having conventional sense amplifier drivers (DRD0 to DRD16) will now be described.
The following is an example for a case in which bank B0 becomes active and while data is being read out of bank B0, bank B2 becomes activated in preparation for data being read out after the read operation from bank B0 is completed. Initially no banks are activated. Initial conditions of address enable signal AE, sense enable signal SE, bank selection signals (BS0 to BS15), bank enable signals (BE0 to BE15), overdrive signal VOP and low sense drive line control signals (SEN0 to SEN16) are all in their not enabled condition and are thus at a logic low. Initial conditions of the high sense drive line control signals (SEP0 to SEP16) are all in their not enabled condition and are thus at a logic high.
First, the semiconductor storage device 1000 can receive a bank activate command to activate bank B0. In the bank activate command an address signal ADR is received which includes a bank address for bank B0, as well as a row address RA. The bank activate command can be received by a command decoder (not shown). The row address activation signal RAA can then be enabled for a predetermined period (a few nanoseconds, as just an example) and timing control circuit 1 can then activate address enable signal AE for a predetermined period (a few nanoseconds, as just an example), thus allowing the row and bank addresses to be latched in row address buffer 2 and bank decoder 3, respectively.
Bank decoder 3 can then activate bank selection signal BS0. With the bank selection signal BS0 activated (logic high in this case), bank enable signal generation circuit EC0 can activate the bank enable signal BE0.
When bank enable signal BEO activated (logic high in this case), row decoder DC0 can decode the row address signal RA and activate the word line specified by the row address signal RA.
When bit lines pairs have achieved a sufficient voltage differential, timing control circuit 1 can place the sense enable signal SE in the enable state (logic high in this case) for a predetermined period (a few nanoseconds, as just an example).
When the sense enable signal SE becomes enabled, sense amplifier rows (SA0 and SA1) provided at opposite sides of the selected bank B0 amplify the potential differences on the bit line pairs and provide a row of data which can be selected by column addresses.
Referring now to FIG. 13, a timing diagram is set forth illustrating the conventional sensing operation. The timing diagram of FIG. 13 includes waveforms for overdrive signal VOP and sense amplifier drive voltage VINTA. The timing diagram of FIG. 13 also includes bank B0 sense signals, such as high sense drive line control signals SEP0/1 (indicating SEP0 and SEP1), low sense drive line control signals SEN0/1 (indicating SEN0 and SEN1), and sense drive lines SAP/N 0/1 (indicating SAP0, SAP1, SAN0, and SAN1). Also included is a bit line pair D/DB 0/1 indicating a complementary bit line pair (D and DB) connected to sense amplifier rows SA0 and SA1, respectively. The timing diagram of FIG. 13 further includes bank B2 sense signals, such as high sense drive line control signals SEP2/3 (indicating SEP2 and SEP3), low sense drive line control signals SEN2/3 (indicating SEN2 and SEN3), and sense drive lines SAP/N 2/3 (indicating SAP2, SAP3, SAN2, and SAN3). Also included is a bit line pair D/DB 2/3 indicating a complementary bit line pair (D and DB) connected to sense amplifier rows SA2 and SA3, respectively.
When sense enable signal SE becomes activated (logic high in this case), pulse generation circuit 4 can set overdrive signal VOP to the overdrive state (logic high) for a predetermined period (for as long as several nanoseconds, for example). During the period in which overdrive signal VOP is in the overdrive state, internal voltage driver 5 overdrives the sense amplifier drive voltage VINTA towards the external power source voltage VCC by providing a low impedance path from sense amplifier drive voltage VINTA to the external power source voltage VCC.
When overdrive signal VOP returns low, the overdrive condition of sense amplifier drive voltage VINTA is terminated. At this time, sense amplifier control circuit SCD0 sets the high sense drive line control signal SEP0 to a low logic level and the low sense drive line control signal SEN0 to a high logic level. At the same time, sense amplifier control circuit SCD1 sets the high sense drive line control signal SEP1 to a low logic level and the low sense drive line control signal SEN1 to a high logic level.
With high sense drive line control signal SEP0 at a logic low level, high sense amplifier drive circuit TRSEP0, shown in FIG. 12, provides a low impedance path between high sense drive line SAP0 and sense amplifier drive voltage VINTA. With high sense drive line control signal SEP1 at a logic low level, high sense amplifier drive circuit TRSEP1, shown in FIG. 12, provides a low impedance path between high sense drive line SAP1 and sense amplifier drive voltage VINTA. With low sense drive line control signal SEN0 at a logic high level, low sense amplifier drive circuit TRSEN0, shown in FIG. 12, provides a low impedance path between low sense drive line SAN0 and low voltage source VSS. With low sense drive line control signal SEN1 at a logic high level, low sense amplifier drive circuit TRSEN1, shown in FIG. 12, provides a low impedance path between low sense drive line SAN1 and low voltage source VSS.
With high and low sense amplifier drive circuits (TRSEP0/1 and TRSEN0/1) activated, high and low sense drive lines (SAP0/1 and SAN0/1) are driven to the sense amplifier drive voltage VINTA and low voltage source VSS, respectively. In this manner sense amplifier rows (SA0 and SA1) become activated and amplify potential differences in each bit line pair of bank B0.
After the sense amplifier rows (SA0 and SA1) have properly sensed data from the selected row of memory cells in bank B0, a column decoder (not illustrated) can decode a received column address. Based on the column address, the column decoder can turn on a column selection switch, which can allow a selected sense amplifier to drive sensed data to an I/O. The data can then propagate through a data amplifier, output buffer and onto an I/O pad to be provided onto a bus external to the bus (none of which is illustrated). Through this process, data is read out from bank B0.
During the time in which bank B0 remains activated, a bank activation command for bank B2 can be received by the semiconductor storage device 1000. Similarly to the bank activation command for bank B0, an address signal ADR specifying the bank (B2) and a row address signal RA is supplied to the semiconductor storage device 1000. Bank B2 can then be activated and data read out in a manner similar to the description above.
Internal voltage driver 5 overdrives the sense amplifier drive voltage VINTA at the beginning of every sensing operation. As show in in FIG. 12, the sense amplifier drive voltage VINTA is shared among the sense amplifier rows (SA0 to SA16). Accordingly, in the semiconductor storage device 1000, using the conventional sensing scheme as shown, the overdriven sense amplifier driving voltage VINTA is supplied to sense amplifier rows (for example SA0 and SA1 as illustrated in FIG. 13) which have already finished their sensing every time another bank (for example B2 as illustrated in FIG. 13) is activated. As a result, voltages levels of the high sense drive lines (SAP0 and SAP1 as illustrated during bank B2 sensing in FIG. 13) are raised to a higher level. This can also cause voltages of bit lines (D/DB 0/1 in FIG. 13) to be raised to a higher level. An increased voltage level on bit lines can lead to reliability problems due to excessive electric fields inducing early breakdown conditions. This can also affect sense margins.
In view of the above discussion, it would be desirable to provide a semiconductor storage device that can have a sense amplifier driving voltage that can have increased current sourcing capabilities at critical sense activation timings. It is desirable to provide the increased current sourcing capabilities without increasing the sense amplifier driving voltage on sense amplifier rows that are already activated even when a plurality of sense amplifier rows share the same sense amplifier driving voltage.
According to the present embodiments, semiconductor storage device includes semse amplifier rows that can receive a common sense amplifier drive voltage applied by an internal voltage driver having a overdrive mode. Semiconductor storage device can include banks of memory cells, row decoders, sense amplifier rows, and sense amplifier drivers. An internal voltage driver can include an overdrive mode, which can be received by a sense amplifier row during an initial portion of a sense operation.
According to one aspect of the embodiments, sense amplifier drivers can include a high sense amplifier drive circuit and a high sense amplifier boost drive circuit. High sense amplifier boost drive circuit can be enabled for a predetermined period during an initial portion of a sense operation and can otherwise be disabled.
According to another aspect of the embodiments, high sense amplifier boost drive circuit can receive a high sense amplifier drive boost control signal. When in a boost enabled state, the high sense amplifier boost control signal can cause a high sense amplifier boost drive voltage to be coupled to a high sense drive line.
According to another aspect of the embodiments, high sense amplifier boost drive voltage can be provided by an internal voltage driver having an overdrive mode in which high sense amplifier boost drive voltage can provide higher current source capabilities and/or a higher voltage potential.
According to another aspect of the embodiments, a pulse generator can generate a boost control signal that places an internal voltage driver in an overdrive mode for a predetermined period at an initial portion of a sense operation.
According to another aspect of the embodiments, high sense amplifier boost drive voltage can be an externally supplied voltage source.
According to another aspect of the embodiments, semiconductor storage device can include a plurality of banks having a predetermined bank address, adjacent banks can share a sense amplifier row.
According to another aspect of the embodiments, semiconductor storage device and have a bank activation mode in which a bank address can be received.
According to another aspect of the embodiments, when a first sense amplifier row is operating in a sense operation timing that is not the initial portion of a sense operation of the first sense amplifier row and a second sense amplifier row is operating in a sense operation timing that is the initial portion of a sense operation for the second sense amplifier row, a first high sense amplifier boost control signal is in the disabled state, a second high sense amplifier boost control signal is in the enabled state, a first high sense amplifier drive control signal is in the enabled state and a second high sense amplifier drive control signal is in the disabled state.
According to another aspect of the embodiments, the high sense amplifier drive circuit and the high sense amplifier boost drive circuit can be a p-channel IGFET.
According to another aspect of the embodiments, a pulse generation circuit generates an overdrive signal and the internal voltage driver is in the overdrive mode when the overdrive signal is in a first logic level and provides a regulated voltage level when the overdrive signal is in a second logic level.